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IJNS
2000
80views more  IJNS 2000»
15 years 6 months ago
VLSI Implementation of Neural Networks
Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more compl...
Bogdan M. Wilamowski, J. Binfet, M. O. Kaynak
ERSA
2010
152views Hardware» more  ERSA 2010»
15 years 4 months ago
Persistent CAD for in-the-field Power Optimization
A major focus within the Integrated Chip (IC) industry is reducing power consumption of devices. In this paper, we explore the idea of persistent CAD algorithms that constantly imp...
Peter Jamieson
ESSCIRC
2011
93views more  ESSCIRC 2011»
14 years 6 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
DAC
2001
ACM
16 years 7 months ago
A True Single-Phase 8-bit Adiabatic Multiplier
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
16 years 3 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani