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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 10 months ago
Thermal and Power Integrity Based Power/Ground Networks Optimization
With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects...
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Pin...
DSD
2006
IEEE
99views Hardware» more  DSD 2006»
15 years 10 months ago
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis m...
Rikard Thid, Ingo Sander, Axel Jantsch
CODES
2001
IEEE
15 years 10 months ago
Hardware/software partitioning of embedded system in OCAPI-xl
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...
Geert Vanmeerbeeck, Patrick Schaumont, Serge Verna...
ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
15 years 10 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
ASPLOS
2010
ACM
15 years 10 months ago
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing
We present an all-optical approach to constructing data networks on chip that combines the following key features: (1) Wavelengthbased routing, where the route followed by a packe...
Nevin Kirman, José F. Martínez