4394 search results - page 452 / 879 » Designing agent chips |
175
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ITC
2003
IEEE
16 years 1 days ago
2003
IEEE
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
144
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ASAP
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
199
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
We present a unified framework that considers flipflop and repeater insertion and the placement of flipflop/repeater blocks during RT or higher level design. We introduce the...
165
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ISCAS
2002
IEEE
2002
IEEE
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
15 years 11 months ago
A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a ...
158
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FPL
2001
Springer
15 years 11 months ago
2001
Springer
Although SRAM programmed Field Programmable Gate Arrays (FPGA's) have come to dominate the industry due to their density and performance advantages over non-volatile technolog...