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GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
16 years 25 days ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
VTS
2006
IEEE
116views Hardware» more  VTS 2006»
16 years 23 days ago
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding
A technique is presented here for improving the compression achieved with any linear decompressor by adding a small non-linear decoder that exploits bit-wise and pattern-wise corr...
Jinkyu Lee, Nur A. Touba
ISCAS
2005
IEEE
147views Hardware» more  ISCAS 2005»
16 years 10 days ago
A two-chip, 4-MHz, microelectromechanical reference oscillator
— The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimize...
Krishnakumar Sundaresan, Paul S. Ho, Siavash Pourk...
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ISQED
2005
IEEE
87views Hardware» more  ISQED 2005»
16 years 10 days ago
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power wit...
Puneet Gupta, Andrew B. Kahng, Puneet Sharma
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
16 years 1 days ago
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise...
Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunse...