4394 search results - page 450 / 879 » Designing agent chips |
174
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GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
154
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration continually increase. Due t...
147
Voted
IPPS
2007
IEEE
16 years 1 months ago
2007
IEEE
Recent advancements in FPGA technology have allowed manufacturers to place general-purpose processors alongside user-configurable logic gates on a single chip. At first glance, ...
153
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FPL
2007
Springer
16 years 28 days ago
2007
Springer
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
146
Voted
DATE
2006
IEEE
16 years 25 days ago
2006
IEEE
Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k tra...