4394 search results - page 398 / 879 » Designing agent chips |
162
click to vote
IPPS
2007
IEEE
16 years 1 months ago
2007
IEEE
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
174
click to vote
VTC
2007
IEEE
16 years 29 days ago
2007
IEEE
Abstract— In this contribution we present a novel ant colony optimization (ACO) based multi-user detector (MUD) designed for synchronous multi-carrier direct sequence code divisi...
166
click to vote
DATE
2006
IEEE
16 years 23 days ago
2006
IEEE
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
171
click to vote
MICRO
2006
IEEE
16 years 21 days ago
2006
IEEE
Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-p...
145
click to vote
ISCAS
2005
IEEE
16 years 8 days ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...