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MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
16 years 1 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
FC
2009
Springer
109views Cryptology» more  FC 2009»
16 years 1 months ago
Optimised to Fail: Card Readers for Online Banking
Abstract. The Chip Authentication Programme (CAP) has been introduced by banks in Europe to deal with the soaring losses due to online banking fraud. A handheld reader is used toge...
Saar Drimer, Steven J. Murdoch, Ross J. Anderson
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
16 years 1 months ago
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can serious...
Fabrizio Mulas, Michele Pittau, Marco Buttu, Salva...
DSN
2008
IEEE
16 years 1 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
ICC
2007
IEEE
140views Communications» more  ICC 2007»
16 years 1 months ago
Performance Analysis of Adaptively-Routed Wormhole-Switched Networks with Finite Buffers
—The use of adaptively-routed wormhole switched k-ary n-cubes has been motivated by the high path diversity provided by the rich topology of this family of interconnection networ...
Nasser Alzeidi, Mohamed Ould-Khaoua, Lewis M. Mack...