4394 search results - page 396 / 879 » Designing agent chips |
185
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CAL
2007
15 years 6 months ago
2007
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
175
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JCM
2008
15 years 6 months ago
2008
With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the perf...
205
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MAM
2007
15 years 6 months ago
2007
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
175
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
185
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will so...