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CODES
2004
IEEE
15 years 10 months ago
Power-aware communication optimization for networks-on-chips with voltage scalable links
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the ener...
Dongkun Shin, Jihong Kim
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
15 years 10 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Floorplan management: incremental placement for gate sizing and buffer insertion
Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental ch...
Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden
DAC
2005
ACM
15 years 8 months ago
TCAM enabled on-chip logic minimization
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eļ¬...
Seraj Ahmad, Rabi N. Mahapatra
ISLPED
2007
ACM
110views Hardware» more  ISLPED 2007»
15 years 8 months ago
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
Fine-grained dynamic voltage/frequency scaling (DVFS) demonstrates great promise for improving the energy-efficiency of chip-multiprocessors (CMPs), which have emerged as a popula...
Sebastian Herbert, Diana Marculescu