Sciweavers

4394 search results - page 293 / 879
» Designing agent chips
Sort
View
DATE
2003
IEEE
176views Hardware» more  DATE 2003»
15 years 11 months ago
Hardware/Software Partitioning of Operating Systems
As MultiProcessor System-on-a-Chip (MPSoC) designs become more common, hardware/software codesign engineers face new challenges involving operating system integration. To speed up...
Vincent John Mooney
EH
2003
IEEE
136views Hardware» more  EH 2003»
15 years 11 months ago
Experimental Results in Evolutionary Fault-Recovery for Field Programmable
This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter (DAC) using the JPL stand-alo...
Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong,...
DSN
2002
IEEE
15 years 11 months ago
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
FPL
2009
Springer
102views Hardware» more  FPL 2009»
15 years 11 months ago
Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...
Rohit Kumar, Ann Gordon-Ross
GECCO
2000
Springer
182views Optimization» more  GECCO 2000»
15 years 10 months ago
A Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits
This paper presents a novel evolvable hardware framework for the automated design of digital circuits for high performance applications. The technique evolves circuits correspondi...
Ben I. Hounsell, Tughrul Arslan