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FPL
2007
Springer
94views Hardware» more  FPL 2007»
16 years 20 days ago
An OCM based shared Memory controller for Virtex 4
In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of ...
Bas Breijer, Filipa Duarte, Stephan Wong
CODES
2005
IEEE
16 years 3 days ago
Future processors: flexible and modular
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...
Charlie Johnson, Jeff Welser
FCCM
2005
IEEE
115views VLSI» more  FCCM 2005»
16 years 3 days ago
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating syst...
John A. Williams, Neil W. Bergmann, X. Xie
ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
16 years 2 days ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
ITC
1998
IEEE
71views Hardware» more  ITC 1998»
15 years 10 months ago
A structured and scalable mechanism for test access to embedded reusable cores
The main objective of core-based IC design is improvement of design efficiency and time-to-market. In order to prevent test development from becoming the bottleneck in the entire ...
Erik Jan Marinissen, Robert G. J. Arendsen, Gerard...