Sciweavers

11242 search results - page 1939 / 2249
» Designing a Super-Peer Network
Sort
View
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
15 years 7 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
BMCBI
2006
128views more  BMCBI 2006»
15 years 6 months ago
An interactive tool for visualization of relationships between gene expression profiles
Background: Application of phenetic methods to gene expression analysis proved to be a successful approach. Visualizing the results in a 3-dimentional space may further enhance th...
Peter Ruzanov, Steven J. M. Jones
CN
2006
85views more  CN 2006»
15 years 6 months ago
A scalable and decentralized fast-rerouting scheme with efficient bandwidth sharing
This paper focuses on the protection of virtual circuits (Label Switched Paths, LSPs) in a (G)MPLS (Generalised Multi-Protocol Label Switching) network. The proposed algorithm is ...
Simon Balon, Laurent Mélon, Guy Leduc
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 6 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
NN
2008
Springer
143views Neural Networks» more  NN 2008»
15 years 6 months ago
A batch ensemble approach to active learning with model selection
Optimally designing the location of training input points (active learning) and choosing the best model (model selection) are two important components of supervised learning and h...
Masashi Sugiyama, Neil Rubens
« Prev « First page 1939 / 2249 Last » Next »