16822 search results - page 793 / 3365 » Designing Simulation Experiments |
239
Voted
ISCA
2006
IEEE
16 years 1 months ago
2006
IEEE
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
208
Voted
RTCSA
2005
IEEE
16 years 1 months ago
2005
IEEE
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing st...
192
Voted
PATMOS
2005
Springer
16 years 1 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
207
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GLVLSI
2003
IEEE
16 years 29 days ago
2003
IEEE
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
194
Voted
ISCA
2002
IEEE
16 years 18 days ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...