16822 search results - page 784 / 3365 » Designing Simulation Experiments |
212
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DAC
2004
ACM
16 years 8 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
153
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VLSID
2003
IEEE
16 years 8 months ago
2003
IEEE
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
198
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VLSID
2003
IEEE
16 years 8 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
174
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ICCD
2005
IEEE
16 years 4 months ago
2005
IEEE
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
181
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ICCAD
2004
IEEE
16 years 4 months ago
2004
IEEE
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the res...