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GLVLSI
2003
IEEE
129views VLSI» more  GLVLSI 2003»
16 years 28 days ago
A system-level methodology for fast multi-objective design space exploration
In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized systems. Since the design space is multi-objective, our aim ...
Gianluca Palermo, Cristina Silvano, S. Valsecchi, ...
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
16 years 17 days ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
DAC
2006
ACM
16 years 8 months ago
Power-centric design of high-speed I/Os
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojan...
DSD
2006
IEEE
110views Hardware» more  DSD 2006»
16 years 1 months ago
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
Ines Viskic, Rainer Dömer
CODES
2004
IEEE
15 years 11 months ago
Benchmark-based design strategies for single chip heterogeneous multiprocessors
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...
JoAnn M. Paul, Donald E. Thomas, Alex Bobrek