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ISCAS
2006
IEEE
128views Hardware» more  ISCAS 2006»
16 years 1 months ago
Modeling and verification of high-speed wired links with Verilog-AMS
—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mi...
Ming-Ta Hsieh, Gerald E. Sobelman
ICCAD
1997
IEEE
53views Hardware» more  ICCAD 1997»
15 years 11 months ago
A quantitative approach to functional debugging
We introduce a novel cut-based debugging paradigm. It coordinates design emulation and simulation and enables fast transition from one to another. Emulation or functional implemen...
Darko Kirovski, Miodrag Potkonjak
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
16 years 8 months ago
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing
Abstract--A novel input and output biasing circuit to extend the input common mode (CM) voltage range and the output swing to rail-to-rail in a low voltage op-amp in standard CMOS ...
S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Pan...
ISQED
2009
IEEE
137views Hardware» more  ISQED 2009»
16 years 2 months ago
Active decap design considerations for optimal supply noise reduction
Active decoupling capacitors (decaps) are more effective than passive decaps at reducing local IR-drop problems in the power distribution network. In the basic active decap, two p...
Xiongfei Meng, Resve A. Saleh
ICASSP
2009
IEEE
16 years 2 months ago
Transceiver design with vector perturbation technique and iterative power loading
— In this paper we consider the optimization of transceivers which use the nonlinear vector perturbation technique at the transmitter. Since the perturbation vector can be almost...
Ching-Chih Weng, P. P. Vaidyanathan