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ISCAS
2002
IEEE
80views Hardware» more  ISCAS 2002»
16 years 6 days ago
FRM based FIR filter design - the WLS approach
Frequency-response masking (FRM) technique produces a filter network which comprises several sub-filters with very sparse coefficient values. If the sub-filters are optimized ...
Ya Jun Yu, Yong Ching Lim
VLSID
1996
IEEE
153views VLSI» more  VLSID 1996»
15 years 11 months ago
Design of high performance two stage CMOS cascode op-amps with stable biasing
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
Pradip Mandal, V. Visvanathan
185
Voted
EURODAC
1994
IEEE
138views VHDL» more  EURODAC 1994»
15 years 11 months ago
A VHDL-based bus model for multi-PCB system design
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo...
ICRA
1995
IEEE
107views Robotics» more  ICRA 1995»
15 years 10 months ago
A Design Method of Local Communication Area in Multiple Mobile Robot System
When many mobile robots should achieve cooperation, local communication system is considered appropriate from the standpoint of the cost and capacity of communication. This paper ...
Eiichi Yoshida, Masakazu Yamamoto, Tamio Arai, Jun...
FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
15 years 8 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong