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DDECS
2006
IEEE
106views Hardware» more  DDECS 2006»
16 years 1 months ago
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the p...
Younggap You, Yong-Dae Kim, Jong Hwa Choi
ICRA
2006
IEEE
131views Robotics» more  ICRA 2006»
16 years 1 months ago
Designing Open-loop Plans for Planar Micro-manipulation
— This paper describes a test-bed for planar micro manipulation tasks and a framework for planning based on quasistatic models of mechanical systems with frictional contacts. We ...
David J. Cappelleri, Jonathan Fink, Barry Munkunda...
EH
2003
IEEE
127views Hardware» more  EH 2003»
16 years 17 days ago
Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits
In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and ...
Carlos A. Coello Coello, Enrique Alba, Gabriel Luq...
ICPP
2000
IEEE
15 years 11 months ago
Issues in Designing and Implementing a Scalable Virtual Interface Architecture
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
Shailabh Nagar, Anand Sivasubramaniam, Jorge Rodri...
ASPDAC
2000
ACM
99views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits
⎯ This paper presents our research results on power-clocked CMOS design. First we provide algebraic expressions and describe properties of clocked signals. Next two types of powe...
Massoud Pedram, Xunwei Wu