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VLSID
1996
IEEE
119views VLSI» more  VLSID 1996»
15 years 11 months ago
Parallel simulated annealing strategies for VLSI cell placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been un...
John A. Chandy, Prithviraj Banerjee
SIGGRAPH
1994
ACM
15 years 11 months ago
The RADIANCE lighting simulation and rendering system
This paper describes a physically-based rendering system tailored to the demands of lighting design and architecture. The simulation uses a light-backwards ray-tracing method with...
Gregory J. Ward
WSC
2007
15 years 9 months ago
SBatch: a spaced batch means procedure for simulation analysis
We discuss SBatch, a simplified procedure for steady-state simulation analysis that is based on spaced batch means, incorporating many advantages of its predecessorsASAP3 and WAS...
Emily K. Lada, James R. Wilson
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 8 months ago
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems
In this paper, we propose a simulation-based methodology for worst-case response time estimation of distributed realtime systems. Schedulability analysis produces pessimistic uppe...
Soheil Samii, Sergiu Rafiliu, Petru Eles, Zebo Pen...
SIMUTOOLS
2008
15 years 8 months ago
DeSiNe: a flow-level QoS simulator of networks
In this paper we present DeSiNe, a modular flow-level network simulator. DeSiNe is aimed at performance analysis and benchmarking of Quality of Service routing algorithms and traf...
Tom Kleiberg, Bingjie Fu, Fernando A. Kuipers, Pie...