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AINA
2007
IEEE
16 years 1 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
ISCIS
2005
Springer
16 years 17 days ago
Characterizing Gnutella Network Properties for Peer-to-Peer Network Simulation
A P2P network that is overlayed over Internet can consist of thousands, or even millions of nodes. To analyze the performance of a P2P network, or an algorithm or protocol designed...
Selim Ciraci, Ibrahim Korpeoglu, Özgür U...
FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
16 years 14 days ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling
DFT
1999
IEEE
119views VLSI» more  DFT 1999»
15 years 11 months ago
RAMSES: A Fast Memory Fault Simulator
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...
Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 10 months ago
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Future Systems-on-Chips will include multiple heterogeneous processing units, with complex data-dependent shared resource access patterns dictating the performance of a design. Cu...
Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, ...