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RTAS
1997
IEEE
15 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
16 years 23 days ago
A simulation methodology for reliability analysis in multi-core SoCs
Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to high...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf...
SIGCSE
2006
ACM
170views Education» more  SIGCSE 2006»
16 years 20 days ago
MARS: an education-oriented MIPS assembly language simulator
We describe the implementation of “MARS,” a GUI, Java-based simulator for the MIPS assembly language. MIPS, the computer architecture underlying the simulated assembly languag...
Kenneth Vollmar, Pete Sanderson
ATAL
2005
Springer
16 years 5 days ago
TACOP: a cognitive agent for a naval training simulation environment
This paper describes how cognitive modeling can be exploited in the design of software agents that support naval training sessions. The architecture, specifications, and embedding...
Willem A. van Doesburg, Annerieke Heuvelink, Egon ...
DAC
2005
ACM
15 years 8 months ago
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
In this paper, we analyze the effect of jitter in track and hold circuits. The output spectrum is obtained in terms of the system function of the track and hold. It is a fairly g...
V. Vasudevan