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CODES
1996
IEEE
15 years 11 months ago
Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated befor...
Jean Paul Calvez, Dominique Heller, Olivier Pasqui...
ATS
2010
IEEE
239views Hardware» more  ATS 2010»
15 years 1 months ago
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
Michael A. Kochte, Christian G. Zoellin, Rafal Bar...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
15 years 11 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
ANSS
1997
IEEE
15 years 11 months ago
JSIM: A JAVA-Based Simulation and Animation Environment
In this paper, we present JSIM, a Java-based simulation and animation environment being developed at the University of Georgia. The JSIM library includes many Java classes to make...
John A. Miller, Rajesh S. Nair, Zhiwei Zhang, Hong...
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 10 months ago
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Santiago González Pestana, Edwin Rijpkema, ...