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DAC
2003
ACM
16 years 7 months ago
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Br...
FM
2003
Springer
136views Formal Methods» more  FM 2003»
15 years 12 months ago
Improving Safety Assessment of Complex Systems: An Industrial Case Study
The complexity of embedded controllers is steadily increasing. This trend, stimulated by the continuous improvement of the computational power of hardware, demands for a correspond...
Marco Bozzano, Antonella Cavallo, Massimo Cifaldi,...
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
ASPDAC
2008
ACM
168views Hardware» more  ASPDAC 2008»
15 years 8 months ago
A fast two-pass HDL simulation with on-demand dump
- Simulation-based functional verification is characterized by two inherently conflicting targets: the signal visibility and simulation performance. Achieving a proper trade-off be...
Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Bai...
DAC
2008
ACM
16 years 7 months ago
Automatic synthesis of clock gating logic with controlled netlist perturbation
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
Aaron P. Hurst