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ET
2002
90views more  ET 2002»
15 years 6 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
JMLR
2010
110views more  JMLR 2010»
15 years 5 months ago
Information Retrieval Perspective to Nonlinear Dimensionality Reduction for Data Visualization
Nonlinear dimensionality reduction methods are often used to visualize high-dimensional data, although the existing methods have been designed for other related tasks such as mani...
Jarkko Venna, Jaakko Peltonen, Kristian Nybo, Hele...
FMCAD
2007
Springer
16 years 23 days ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony
TIME
2007
IEEE
16 years 26 days ago
Multilingual Extension of Temporal Expression Recognition Using Parallel Corpora
This paper presents the automatic extension of TERSEO to other languages, a knowledge-based system for the recognition and normalization of temporal expressions, originally develo...
Marcel Puchol-Blasco, Estela Saquete, Patricio Mar...
IAT
2003
IEEE
15 years 12 months ago
Web Course Self-Adaptation
This paper describes the methodology of an intelligent agent for building a self-adaptive course on the Web. An important task, therefore, is to combine adaptability with the lear...
Mohammed Abdel Razek, Claude Frasson, Marc Kaltenb...