Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
Nonlinear dimensionality reduction methods are often used to visualize high-dimensional data, although the existing methods have been designed for other related tasks such as mani...
Jarkko Venna, Jaakko Peltonen, Kristian Nybo, Hele...
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
This paper presents the automatic extension of TERSEO to other languages, a knowledge-based system for the recognition and normalization of temporal expressions, originally develo...
This paper describes the methodology of an intelligent agent for building a self-adaptive course on the Web. An important task, therefore, is to combine adaptability with the lear...
Mohammed Abdel Razek, Claude Frasson, Marc Kaltenb...