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DAC
2006
ACM
16 years 7 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
DAC
2004
ACM
16 years 7 months ago
Automatic generation of breakpoint hardware for silicon debug
Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpo...
Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep...
HICSS
2008
IEEE
181views Biometrics» more  HICSS 2008»
16 years 1 months ago
Systems Theory Model for Information Security
Architecting security solutions for today’s diverse computer systems is a challenge. The modern business environment is comprised of many different applications, e-mail, databas...
Wm. Arthur Conklin, Glenn B. Dietrich
ICRA
2005
IEEE
90views Robotics» more  ICRA 2005»
16 years 5 days ago
Genetic Optimization and Simulation of a Piezoelectric Pipe-Crawling Inspection Robot
- Using the Darwin2k development software, a genetic algorithm (GA) was used to design and optimize a pipecrawling robot for parameters such as mass, power consumption, and joint e...
Geoffrey Hollinger, Jeri Briscoe
CAV
1999
Springer
92views Hardware» more  CAV 1999»
15 years 11 months ago
Latency Insensitive Protocols
The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of In...
Luca P. Carloni, Kenneth L. McMillan, Alberto L. S...