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ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
16 years 1 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
GLOBECOM
2006
IEEE
16 years 16 days ago
Performance Analysis and Optimal Signal Designs for Minimum Decoding Complexity ABBA Codes
— ABBA codes, a class of quasi-orthogonal space-time block codes (STBC) proposed by Tirkkonen et al., have been studied extensively for various applications. Yuen et al. have rec...
Dung Ngoc Dao, Chintha Tellambura
GECCO
2006
Springer
207views Optimization» more  GECCO 2006»
15 years 10 months ago
Both robust computation and mutation operation in dynamic evolutionary algorithm are based on orthogonal design
A robust dynamic evolutionary algorithm (labeled RODEA), where both the robust calculation and mutation operator are based on an orthogonal design, is proposed in this paper. Prev...
Sanyou Y. Zeng, Rui Wang, Hui Shi, Guang Chen, Hug...
GLVLSI
2007
IEEE
107views VLSI» more  GLVLSI 2007»
16 years 24 days ago
Side-channel resistant system-level design flow for public-key cryptography
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design st...
Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingr...
DATE
2006
IEEE
83views Hardware» more  DATE 2006»
16 years 16 days ago
What lies between design intent coverage and model checking?
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that ca...
Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. ...