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ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
16 years 3 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
16 years 3 months ago
Fast and accurate transaction level models using result oriented modeling
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
Gunar Schirner, Rainer Dömer
TLDI
2009
ACM
142views Formal Methods» more  TLDI 2009»
16 years 3 months ago
Static extraction of sound hierarchical runtime object graphs
For many object-oriented systems, it is often useful to have a runtime architecture that shows networks of communicating objects. But it is hard to statically extract runtime obje...
Marwan Abi-Antoun, Jonathan Aldrich
ICS
2009
Tsinghua U.
16 years 1 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
ICPP
2009
IEEE
16 years 1 months ago
Load Balance in the Phylogenetic Likelihood Kernel
—Recent advances in DNA sequencing techniques have led to an unprecedented accumulation and availability of molecular sequence data that needs to be analyzed. This data explosion...
Alexandros Stamatakis, Michael Ott