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FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
15 years 8 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang
GECCO
2008
Springer
146views Optimization» more  GECCO 2008»
15 years 7 months ago
A formal performance modeling framework for bio-inspired ad hoc routing protocols
Bio-inspired ad hoc routing is an active area of research. The designers of these algorithms predominantly evaluate the performance of their protocols with the help of simulation ...
Muhammad Saleem, Syed Ali Khayam, Muddassar Farooq
GPCE
2008
Springer
15 years 7 months ago
Property models: from incidental algorithms to reusable components
A user interface, such as a dialog, assists a user in synthesising a set of values, typically parameters for a command object. Code for “command parameter synthesis” is usuall...
Jaakko Järvi, Mat Marcus, Sean Parent, John F...
DAC
2010
ACM
15 years 6 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
CCS
2010
ACM
15 years 6 months ago
Modeling attacks on physical unclonable functions
We show in this paper how several proposed Physical Unclonable Functions (PUFs) can be broken by numerical modeling attacks. Given a set of challenge-response pairs (CRPs) of a PU...
Ulrich Rührmair, Frank Sehnke, Jan Sölte...