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» Design techniques for low-power systems
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ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
15 years 12 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 11 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
CORR
2008
Springer
96views Education» more  CORR 2008»
15 years 6 months ago
High Efficiency 3-Phase Cmos Rectifier with Step Up and Regulated
: This paper presents several design issues related to the monolithic integration of a 3-phase AC to DC low voltage, low power rectifier for 3-phase micro source electrical conditi...
J.-C. Crebier, Y. Lembeye, H. Raisigel, O. Deleage...
ICCAD
1995
IEEE
97views Hardware» more  ICCAD 1995»
15 years 9 months ago
Interface co-synthesis techniques for embedded systems
A key aspect of the synthesis of embedded systems is the automatic integration of system components. This entails the derivation of both the hardware and software interfaces that ...
Pai H. Chou, Ross B. Ortega, Gaetano Borriello
ISCAS
1999
IEEE
70views Hardware» more  ISCAS 1999»
15 years 10 months ago
A new multipath amplifier design technique for enhancing gain without sacrificing bandwidth
A new multistage multipath amplifier design technique is introduced that combines the formerly distinct phases of stage design and compensation. The result is an inherently stable...
M. E. Schlarmann, E. K. F. Lee, Randall L. Geiger