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HPCA
2011
IEEE
14 years 10 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISLPED
2010
ACM
170views Hardware» more  ISLPED 2010»
15 years 6 months ago
Low-power sub-threshold design of secure physical unclonable functions
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnapp...
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
15 years 4 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
16 years 22 days ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
HPDC
1999
IEEE
15 years 10 months ago
Techniques for Automating Distributed Real-Time Applications Design
We present a performance-based methodology for designing a high-bandwidth radar application on commodity platforms. Unlike many real-time systems, our approach works for commodity...
Dong-In Kang, Richard Gerber, Leana Golubchik, Jef...