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DAC
2005
ACM
15 years 8 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
HPCA
2005
IEEE
15 years 12 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ASPDAC
1995
ACM
104views Hardware» more  ASPDAC 1995»
15 years 9 months ago
Power analysis of a 32-bit embedded microcontroller
A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...
Vivek Tiwari, Mike Tien-Chien Lee
ICIP
2010
IEEE
15 years 4 months ago
Joint color decrosstalk and demosaicking for CFA cameras
In interest of low cost, low power consumption, and compact size, most digital cameras adopt a design of single sensor array coupled with a color filter array. This design inevita...
Xiaolin Wu, Xiangjun Zhang
DAC
2006
ACM
16 years 7 months ago
Low-power bus encoding using an adaptive hybrid algorithm
In this paper, we propose an adaptive low-power bus encoding algorithm based on weighted code mapping (WCM) and the delayed bus technique. The WCM algorithm transforms an original...
Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru...