Sciweavers

5672 search results - page 32 / 1135
» Design techniques for low-power systems
Sort
View
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
15 years 9 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
DATE
2007
IEEE
156views Hardware» more  DATE 2007»
16 years 10 days ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
16 years 2 months ago
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Du...
INFOCOM
2007
IEEE
16 years 9 days ago
Low-Power Distributed Event Detection in Wireless Sensor Networks
Abstract—In this paper we address the problem of energyefficient event detection in wireless sensor networks (WSNs). Duty cycling is a fundamental approach to conserving energy i...
Yanmin Zhu, Yunhao Liu, Lionel M. Ni, Z. Zhang
ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
15 years 11 months ago
Low power coordination in wireless ad-hoc networks
Distributed wireless ad-hoc networks (DWANs) pose numerous technical challenges. Among them, two are widely considered as crucial: autonomous localized operation and minimization ...
Farinaz Koushanfar, Abhijit Davare, Dai Tho Nguyen...