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DAC
2005
ACM
16 years 7 months ago
Logic block clustering of large designs for channel-width constrained FPGAs
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
Marvin Tom, Guy G. Lemieux
SIGMOD
2006
ACM
150views Database» more  SIGMOD 2006»
16 years 6 months ago
Automatic physical design tuning: workload as a sequence
The area of automatic selection of physical database design to optimize the performance of a relational database system based on a workload of SQL queries and updates has gained p...
Sanjay Agrawal, Eric Chu, Vivek R. Narasayya
ICRA
2002
IEEE
127views Robotics» more  ICRA 2002»
15 years 11 months ago
Design and Control of a Three-Link Serial Manipulator for Lessons in Particle Dynamics
Design, control, and performance of a ball-throwing robot are examined in this paper. The objective of this project is to provide an interactive ball-throwing robotic arm for illu...
Mark A. Minor, Kent Jensen, Youngshik Kim
VRML
1998
ACM
15 years 11 months ago
3D Product Presentation Online: The Virtual Design Exhibition
VRML offers a high potential for product presentation: Instead of regarding flat, static pictures, configurable and animated 3D models embedded in entertaining environments provid...
J. Dauner, Jürgen Landauer, E. Stimpfig, D. R...
DAC
2005
ACM
15 years 8 months ago
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technolog...
Subhasish Mitra, Tanay Karnik, Norbert Seifert, Mi...