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ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
16 years 5 days ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 12 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ICCBSS
2004
Springer
15 years 12 months ago
First International Workshop on Incorporating COTS into Software Systems
Abstract. This workshop explores innovative ways of integrating COTS software into software systems for purposes often unimagined by their original designers. It emphasizes tools a...
Alexander Egyed, Dewayne E. Perry
NAACL
2010
15 years 4 months ago
Crowdsourcing the evaluation of a domain-adapted named entity recognition system
Named entity recognition systems sometimes have difficulty when applied to data from domains that do not closely match the training data. We first use a simple rule-based techniqu...
Asad B. Sayeed, Timothy J. Meyer, Hieu C. Nguyen, ...
ICASSP
2008
IEEE
16 years 1 months ago
Blind channel estimation in DS-CDMA systems with unknown wide-sense stationary noise using generalized correlation decomposition
A novel blind subspace-based channel estimation technique is developed for direct-sequence code division multiple-access (DS-CDMA) systems operating in unknown wide-sense stationa...
Keyvan Zarifi, Alex B. Gershman