Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
Abstract. This workshop explores innovative ways of integrating COTS software into software systems for purposes often unimagined by their original designers. It emphasizes tools a...
Named entity recognition systems sometimes have difficulty when applied to data from domains that do not closely match the training data. We first use a simple rule-based techniqu...
Asad B. Sayeed, Timothy J. Meyer, Hieu C. Nguyen, ...
A novel blind subspace-based channel estimation technique is developed for direct-sequence code division multiple-access (DS-CDMA) systems operating in unknown wide-sense stationa...