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ASPDAC
2006
ACM
110views Hardware» more  ASPDAC 2006»
16 years 26 days ago
Switching-activity driven gate sizing and Vth assignment for low power design
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
ISLPED
2005
ACM
99views Hardware» more  ISLPED 2005»
16 years 13 days ago
A low-power bus design using joint repeater insertion and coding
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
Srinivasa R. Sridhara, Naresh R. Shanbhag
IWQOS
2005
Springer
16 years 11 days ago
Designing a Predictable Internet Backbone with Valiant Load-Balancing
Abstract. Network operators would like their network to support current and future traffic matrices, even when links and routers fail. Not surprisingly, no backbone network can do ...
Rui Zhang-Shen, Nick McKeown
SAC
2004
ACM
16 years 9 days ago
DSPxPlore: design space exploration methodology for an embedded DSP core
High mask and production costs for the newest CMOS silicon technologies increase the pressure to develop hardware platforms useable for different applications or variants of the s...
Christian Panis, Ulrich Hirnschrott, Gunther Laure...
CTRSA
2004
Springer
114views Cryptology» more  CTRSA 2004»
16 years 8 days ago
Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems
This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduce...
Lejla Batina, Geeke Bruin-Muurling, Siddika Berna ...