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ITNG
2007
IEEE
16 years 1 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
ICC
2009
IEEE
162views Communications» more  ICC 2009»
16 years 1 months ago
Design and Evaluation of a Multilevel Decoder for Satellite Communications
—In this paper, we propose a multilevel coding (MLC) scheme suitable for satellite communications, where different QoS levels are required. We introduce a novel characterization ...
Aharon Vargas, Marco Breiling, Wolfgang H. Gerstac...
TCAD
2008
84views more  TCAD 2008»
15 years 6 months ago
Buffering Interconnect for Multicore Processor Designs
Recently, the microprocessor industry is headed in the direction of multicore designs in order to continue the chip performance growth. We investigate buffer insertion, which is a ...
Yifang Liu, Jiang Hu, Weiping Shi
DATE
2009
IEEE
107views Hardware» more  DATE 2009»
16 years 1 months ago
User-centric design space exploration for heterogeneous Network-on-Chip platforms
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
Chen-Ling Chou, Radu Marculescu
ITIIS
2010
144views more  ITIIS 2010»
15 years 5 months ago
Cross-layer Design of Rate and Quality Adaptation Schemes for Wireless Video Streaming
Video streaming service over wireless networks is a challenging task because of the changes in the wireless channel conditions that can occur due to interference, fading, and stat...
Sunhun Lee, Kwangsue Chung