8093 search results - page 374 / 1619 » Design optimization |
173
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CHES
2009
Springer
16 years 7 months ago
2009
Springer
Abstract. This paper presents a design-space exploration of an applicationspecific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barre...
171
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ASPDAC
2009
ACM
16 years 1 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
202
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ARC
2010
Springer
15 years 7 months ago
2010
Springer
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
198
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DCOSS
2005
Springer
16 years 10 days ago
2005
Springer
In wireless sensor networks, energy and communication bandwidth are precious resources. Traditionally, layering has been used as a design principle for network stacks; hence routin...
208
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ESTIMEDIA
2005
Springer
16 years 10 days ago
2005
Springer
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...