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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
16 years 1 months ago
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang...
TSP
2008
99views more  TSP 2008»
15 years 6 months ago
Adaptive Polarized Waveform Design for Target Tracking Based on Sequential Bayesian Inference
Abstract--In this paper, we develop an adaptive waveform design method for target tracking under a framework of sequential Bayesian inference. We employ polarization diversity to i...
Martin Hurtado, Tong Zhao, Arye Nehorai
ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
16 years 7 days ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
CN
2004
109views more  CN 2004»
15 years 6 months ago
Modeling correlations in web traces and implications for designing replacement policies
A number of web cache-related algorithms, such as replacement and prefetching policies, rely on specific characteristics present in the sequence of requests for efficient performa...
Konstantinos Psounis, An Zhu, Balaji Prabhakar, Ra...