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RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
16 years 8 days ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
ACNS
2005
Springer
94views Cryptology» more  ACNS 2005»
16 years 7 days ago
Optimal Asymmetric Encryption and Signature Paddings
Strong security notions often introduce strong constraints on the construction of cryptographic schemes: semantic security implies probabilistic encryption, while the resistance to...
Benoît Chevallier-Mames, Duong Hieu Phan, Da...
DAC
1999
ACM
16 years 7 months ago
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
ICCD
2008
IEEE
191views Hardware» more  ICCD 2008»
16 years 3 months ago
Energy-delay tradeoffs in 32-bit static shifter designs
—This paper compares the energy-delay tradeoff curves of 32-bit static barrel and funnel shifters. The Stanford Circuit Optimization Tool (SCOT) is used to determine best transis...
Steven Huntzicker, Michael Dayringer, Justin Sopra...
ICRA
2009
IEEE
118views Robotics» more  ICRA 2009»
16 years 1 months ago
Design and implementation of a 9-axis inertial measurement unit
— We report on a 9-axis inertial measurement unit (IMU) which utilizes 3-axis angular velocity measurements from rate gyros and 6-axis linear acceleration measurements from three...
Pei-Chun Lin, Chi-Wei Ho