Sciweavers

8093 search results - page 1540 / 1619
» Design optimization
Sort
View
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
16 years 1 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
PPOPP
2010
ACM
16 years 1 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...
SAC
2010
ACM
16 years 1 months ago
Adaptive internet services through performance and availability control
Cluster-based multi-tier systems provide a means for building scalable Internet services. Building adaptive Internet services that are able to apply appropriate system sizing and ...
Jean Arnaud, Sara Bouchenak
IPSN
2010
Springer
16 years 1 months ago
User-centric radio power control for opportunistic mountain hiking networks
bstract: User-Centric Radio Power Control for Opportunistic Mountain Hiking Networks ∗ Jyh-How Huang1 , Po-Yen Lin1 , Yu-Te Huang2 , Seng-Yong Lau1 , Ling-Jyh Chen2 , Kun-chan La...
Jyh-How Huang, Po-Yen Lin, Yu-Te Huang, Seng-Yong ...
LCTRTS
2010
Springer
16 years 1 months ago
Sampling-based program execution monitoring
For its high overall cost during product development, program debugging is an important aspect of system development. Debugging is a hard and complex activity, especially in time-...
Sebastian Fischmeister, Yanmeng Ba
« Prev « First page 1540 / 1619 Last » Next »