8093 search results - page 1369 / 1619 » Design optimization |
184
click to vote
FPGA
1998
ACM
15 years 11 months ago
1998
ACM
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...
160
click to vote
ICCAD
1997
IEEE
15 years 10 months ago
1997
IEEE
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
184
click to vote
GLVLSI
1996
IEEE
15 years 10 months ago
1996
IEEE
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
216
click to vote
ARITH
1993
IEEE
15 years 10 months ago
1993
IEEE
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
142
click to vote
EURODAC
1994
IEEE
15 years 10 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...