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» Design of the MUC-6 evaluation
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ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen
GI
2009
Springer
15 years 4 months ago
An Improved Method for creating Shared Belief in Communication Constrained Sensor Networks
: Networked systems that gather sensor data in order to react to phenomena in their surroundings are faced with a growing need for adaptive behavior to operate in dynamically chang...
Eelke van Foeken, Peter Hiemstra, Leon Kester
IEEEPACT
2007
IEEE
16 years 1 months ago
FAME: FAirly MEasuring Multithreaded Architectures
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...
Javier Vera, Francisco J. Cazorla, Alex Pajuelo, O...
SIGIR
1996
ACM
15 years 10 months ago
Evaluation of a Tool for Visualization of Information Retrieval Results
We report on the design and evaluation of a visualization tool for Information Retrieval (IR) systems that aims to help the end user in the following respects:
Aravindan Veerasamy, Nicholas J. Belkin
IJES
2008
83views more  IJES 2008»
15 years 6 months ago
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures
Reconfigurable ALU Array (RAA) architectures--representing a popular class of Coarse-grained Reconfigurable Architectures--are gaining in popularity especially for media applicati...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt