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ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
16 years 1 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 20 days ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
15 years 12 months ago
Automated Bus Generation for Multiprocessor SoC Design
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
Kyeong Keol Ryu, Vincent John Mooney
VRML
2003
ACM
15 years 12 months ago
3D virtual clothing: from garment design to web3d visualization and simulation
One of the major challenges in Computer Graphics concerns the 3D representation and physically-based simulation of garments. In our research, we are working closely with the texti...
Luca Chittaro, Demis Corvaglia
ICSR
2011
Springer
14 years 10 months ago
Improving Product Line Architecture Design and Customization by Raising the Level of Variability Modeling
Product Line Architecture (PLA) plays a central role in software product line development. In order to support architecture-level variability modeling, most architecture descriptio...
Jiayi Zhu, Xin Peng, Stan Jarzabek, Zhenchang Xing...