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» Design of the MUC-6 evaluation
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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 10 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
SIGSOFT
2004
ACM
16 years 7 months ago
Reasoning about partial goal satisfaction for requirements and design engineering
Exploring alternative options is at the heart of the requirements and design processes. Different alternatives contribute to different degrees of achievement of non-functional goa...
Emmanuel Letier, Axel van Lamsweerde
WWW
2007
ACM
16 years 7 months ago
C-ODO: an OWL Meta-model for Collaborative Ontology Design
The design and maintenance of ontologies is a complex social collaborative activity, and this is true especially for semantic-web ontologies. On the one hand, such activity calls ...
Aldo Gangemi, Jos Lehmann, Valentina Presutti, Mal...
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
16 years 1 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras
CODES
2005
IEEE
16 years 8 days ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair