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ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
16 years 1 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
16 years 10 days ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
MATA
2004
Springer
199views Communications» more  MATA 2004»
16 years 3 days ago
Configuration Management for Networked Reconfigurable Embedded Devices
Distribution of product updates to embedded devices can increase product lifetimes for consumers and boost revenues for vendors. Dynamic provisioning of application solutions to e...
Timothy O'Sullivan, Richard Studdert
DFT
2003
IEEE
132views VLSI» more  DFT 2003»
16 years 1 days ago
Level-Hybrid Optoelectronic TESH Interconnection Network
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
Vijay K. Jain, Glenn H. Chapman
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
15 years 12 months ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...