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MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
16 years 22 days ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 11 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
UM
2009
Springer
16 years 29 days ago
Performance Evaluation of a Privacy-Enhancing Framework for Personalized Websites
Abstract. Reconciling personalization with privacy has been a continuing interest in the user modeling community. In prior work, we proposed a dynamic privacy-enhancing user modeli...
Yang Wang 0005, Alfred Kobsa
LOCA
2005
Springer
15 years 12 months ago
The COMPASS Location System
The aim of COMPASS (short for COM mon Positioning Architecture for Several Sensors) is to realize a location infrastructure which can make use of a multitude of different sensors,...
Frank Kargl, Alexander Bernauer
TOOLS
1998
IEEE
15 years 10 months ago
Implementation of a Geospatial Imagery Digital Library Using Java and CORBA
We have implemented a prototype distributed system for managing and accessing a digital library of geospatial imagery over a wide-area network. The system conforms to a subset of ...
Paul D. Coddington, Kenneth A. Hawick, K. E. Kerry...
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