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» Design of Synchronous Action Systems
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CODES
2002
IEEE
15 years 11 months ago
Worst-case performance analysis of parallel, communicating software processes
In this paper we present a method to perform static timing analysis of SystemC models, that describe parallel, communicating software processes.The paper combines a worstcase exec...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 10 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
15 years 10 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
SIAMCOMP
2000
66views more  SIAMCOMP 2000»
15 years 6 months ago
Computations of Uniform Recurrence Equations Using Minimal Memory Size
We consider a system of uniform recurrence equations (URE) of dimension one. We show how its computation can be carried out using minimal memory size with several synchronous proc...
Bruno Gaujal, Alain Jean-Marie, Jean Mairesse
TOCS
2012
13 years 8 months ago
A File Is Not a File: Understanding the I/O Behavior of Apple Desktop Applications
We analyze the I/O behavior of iBench, a new collection of productivity and multimedia application workloads. Our analysis reveals a number of differences between iBench and typic...
Tyler Harter, Chris Dragga, Michael Vaughn, Andrea...