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» Design of Neuromorphic Hardwares
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ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
16 years 3 months ago
High-level synthesis: an essential ingredient for designing complex ASICs
It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog will incur a performance penalty. The case study here shows that this need not be the ca...
Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, N...
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
16 years 1 months ago
Partition-based exploration for reconfigurable JPEG designs
Philip G. Potter, Wayne Luk, Peter Y. K. Cheung
DATE
2008
IEEE
84views Hardware» more  DATE 2008»
16 years 25 days ago
On the Verification of High-Order Constraint Compliance in IC Design
Jan B. Freuer, Göran Jerke, Joachim Gerlach, ...
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
16 years 25 days ago
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor
Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Ta...
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
16 years 21 days ago
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Paul Wielage, Erik Jan Marinissen, Michel Altheime...