8345 search results - page 1607 / 1669 » Design of Neuromorphic Hardwares |
179
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PLDI
1994
ACM
15 years 10 months ago
1994
ACM
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
184
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CF
2007
ACM
15 years 10 months ago
2007
ACM
In this paper we describe a new technique, called pipeline spectroscopy, and use it to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogra...
218
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
156
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
162
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FCCM
2007
IEEE
15 years 10 months ago
2007
IEEE
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...