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» Design of Neuromorphic Hardwares
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IPPS
2000
IEEE
15 years 10 months ago
Study of a Multilevel Approach to Partitioning for Parallel Logic Simulation
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
Swaminathan Subramanian, Dhananjai Madhava Rao, Ph...
SIGCOMM
2000
ACM
15 years 10 months ago
SmartBridge: A scalable bridge architecture
As the number of hosts attached to a network increases beyond what can be connected by a single local area network (LAN), forwarding packets between hosts on different LANs become...
Thomas L. Rodeheffer, Chandramohan A. Thekkath, Da...
SPAA
2000
ACM
15 years 10 months ago
DCAS-based concurrent deques
The computer industry is currently examining the use of strong synchronization operations such as double compareand-swap (DCAS) as a means of supporting non-blocking synchronizati...
Ole Agesen, David Detlefs, Christine H. Flood, Ale...
REST
2010
ACM
15 years 10 months ago
A RESTful messaging system for asynchronous distributed processing
Traditionally, distributed computing problems have been solved by partitioning data into chunks able to be handled by commodity hardware. Such partitioning is not possible in case...
Ian Jacobi, Alexey Radul
ARITH
1999
IEEE
15 years 10 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
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